| Title | : | Application-driven future supercomputing |
| Speaker | : | Dirk Pleiter and Wouter Klijn (University of Regensburg. Germany) |
| Details | : | Thu, 1 Dec, 2016 10:00 AM @ BSB 361 |
| Abstract: | : | From tera-, peta- to exascale, supercomputing capabilities seem to evolve steadily to the next performance level. Reaching next performance levels will become more difficult due to power constraints and the related challenge of maintaining processing and data transport capabilities. This is particular critical for emerging application areas, e.g. life sciences. We will present selected requirements from a specific application area, namely brain research. The European Human Brain Project allowed us to obtain early experiences with two future supercomputing swim lines: homogeneous many-core architectures versus heterogeneous GPU-accelerated architectures. We will in particular focus on the OpenPOWER roadmaps based on fat servers with POWER processors that are accelerated by GPUs. Biography of the Speakers : Dirk Pleiter Prof. Dr. Dirk Pleiter is research group leader at the Jülich Supercomputing Centre (JSC) and professor of theoretical physics at the University of Regensburg. At JSC he is leading the work on application oriented technology development. Currently he is principal investigator of the POWER Acceleration and Design Center and the NVIDIA application Lab at Jülich. He has played a leading role in several projects for developing massively-parallel special purpose computers, including QPACE. He is acting as work package leader in several H2020 FETHPC projects, namely SAGE and ExaNoDe, as well as in the Human Brain Project (HBP). Wouter Klijn Wouter Klijn MSc. is a research assistant at the Simulation Laboratory Neuroscience part of the Jülich Supercomputing Centre (JSC) and PhD student in computational neuroscience. At the simlab he supports neuroscientists in deploying and optimize existing software for current and future HPC hardware. Within the HBP he is part of the developer team implementing NestMC, a next generation multicompartment neural network simulator specifically written for "many-core" architectures such as GPU and Intel Xeon Phi based systems. His PhD research focuses on large scale spiking neural network dynamics. |
